What you'll learn
ISA (RISC vs CISC)
CPU Datapath & Control
Pipelining & Hazards
Memory Hierarchy & Cache
Virtual Memory
Multicore Architectures
W1
Instruction Set Architecture (ISA)
Analyze the hardware-software interface and assembly language.
2 videos•18m
3 readings
2 topics
1 homework
W2
CPU Datapath and Control
Trace instruction execution through the CPU datapath.
2 videos•63m
3 readings
2 topics
1 homework
W3
Instruction Pipelining
Improve throughput using pipelining and hazard resolution.
2 videos•25m
3 readings
2 topics
1 homework
W4
Advanced CPU Design
Understand ILP and superscalar architectures.
2 videos•29m
3 readings
2 topics
1 homework
W5
Cache and Memory Hierarchy
Optimize memory access using caching mechanisms.
2 videos•24m
3 readings
2 topics
1 homework
W6
Virtual Memory and OS Interaction
Translate virtual addresses to physical addresses using page tables.
2 videos•24m
3 readings
2 topics
1 homework
W7
Multicore and Parallel Processing
Understand cache coherence in multicore processors.
2 videos•59m
3 readings
2 topics
1 homework
01
Learn
Watch curated videos and read study resources
02
Practice
Practice what you learned
03
Build Projects
Build projects using your new gained knowledge
04
Submit & Verify
Submit your project and get verified by our system
References
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